PERC Rule Deck Development Engineer
Intel, India, Bangalore
The role
We are looking for a PERC Runset Development Engineer to develop and Validate PERC (Programmable Electrical Rule Checker) rule decks. The role involves working closely with PDK Team and foundry to implement PERC and ensure design compliance.
What you will do
- Rule Development: Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations (e.g., ESD paths, current density, voltage stress, and floating gates).
- Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between Calibre PERC( preferred), Cadence Pegasus, and Synopsys tools.
- Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules.
- Debug and Analysis: Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives.