Principal Physical Verification Engineer
Broadcom, USA-CA San Jose Innovation Drive
What you will do
- Execution of Chip level Physical Verification & Issue resolution
- Work on setting up DRM runsets for advance nodes and tool flows
- Manage and guide rules related to Top level Floorplan, I/O and bump planning
- Resolve physical design issues related to chip integration and assembly
- Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
- Develop best practice guidelines for physical verification flows and runtime optimizations