ASIC Emulation & Verification Engineer
Broadcom, USA-CA San Jose Innovation Drive
What you will do
- Palladium Emulation & Bring-up: Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems. Resolve compilation errors, manage clocking/memory overrides, and successfully bring up full-chip and sub-system emulation models.
- Firmware Co-Verification: Partner closely with firmware engineering teams to accelerate early FW bring-up on the Palladium platform. Provide hardware models, map memory spaces, and configure virtual debuggers (like JTAG) to allow teams to boot low-level bootloaders, drivers, and operating systems well before physical silicon is available.