- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
- At least 5 years of relevant design verification experience at the unit, subsystem, or SoC level.
- Hands-on experience with Cadence Palladium or a comparable hardware emulation platform, including environment bring-up, regression execution, failure triage, and debug.
- Strong C/C++ programming skills, with experience developing verification models, test infrastructure, or hardware validation tests.
- Strong SystemVerilog skills and experience building verification environments using UVM.
- Experience with constrained-random stimulus, functional coverage, assertions, and coverage closure.
- Strong debugging and analytical skills, including isolating emulation failures and reproducing issues in simulation.
Ways to stand out from the crowd
- Direct experience bringing up and debugging SerDes IP or subsystems on Cadence Palladium.
- Experience adapting UVM testbenches, C/C++ models, and mixed-signal behavioral models for efficient emulation.
- Experience developing SerDes RNM models and correlating their behavior with analog simulation results or silicon measurements.
- Understanding of SerDes architectures, mixed-signal interfaces, calibration, adaptation, and link training.
- Expertise in high-speed protocols such as PCI Express, USB, or SATA.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 10, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.