- BS or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science; advanced degrees (MS, PhD) are a plus.
- 5+ years of experience in ASIC verification-related fields at both the IP and SoC level.
- Proven experience in building UVM testbenches from scratch and applying constrained random methodology in a production environment.
- High proficiency in C/C++ with the ability to develop architectural golden models and hardware-software co-verification tests.
- Deep domain knowledge in Low-Speed IOs (QSPI, UART, I2C), High-Speed IOs (Ethernet), AXI/APB interconnects, DMA controllers, and Memory Controllers.
- Expert skills in assertion-based design checks (SVA), code coverage, functional coverage, and formal test plan documentation.
- Strong debugging and analytical skills with a methodical approach to resolving complex SoC-level corner cases.
- Professional-grade scripting abilities in Python, Perl, or TCL to automate build flows and regressions.
Ways to Stand Out from the Crowd
- Advanced UVM architecture knowledge and large-scale SoC verification experience is a plus!
- A forward-thinking mindset with a demonstrated ability to use AI tools to accelerate engineering tasks.
- Experience with Testbench Build flows, Makefiles, and version control (Perforce).
- Ambitious, highly motivated, and a strong desire to work as a collaborative teammate in a fast-paced environment.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.