Staff Engineer- DFT
Marvell, Santa Clara, CA
What you need
- BS/MS in EE/CE; 5+ years of DFT experience, MS in EE/CE: 3+ years of experience
- Hands-on with scan/ATPG/MBIST/JTAG using Synopsys or Siemens tools.
- Good Verilog/SystemVerilog and scripting (Tcl/Python/Perl) skills.
- Understanding of ASIC flow, STA, and gate-level simulation.
- Good communication; works well in cross-functional teams.
Expected Base Pay Range (USD) 113,920 – 170,600, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.