Principal Engineer, DFT
Marvell, Bangalore
What you need
What We're Looking For
We are seeking a highly motivated and experienced Principal Engineer – Design for Test (DFT) to lead DFT architecture, implementation, and signoff activities for complex SoC and ASIC designs. The ideal candidate will have deep expertise in DFT methodologies, scan insertion, ATPG, timing constraints, and test architecture development, with a proven track record of delivering high-quality silicon products.
Required Qualifications
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field.
- 14+ years of experience in Design for Test (DFT) for ASIC/SoC development.
- Strong expertise in DFT methodologies, including scan architecture, scan compression, ATPG, Memory BIST, Boundary Scan and testability concepts.
- Hands-on experience with Siemens EDA Tessent tools.
- Strong experience with synthesis and scan insertion tools.