Principal DFT Engineer

Fortell, San Francisco Bay Area, CA

What you will do

Develop, architect and implement comprehensive DFT structures tailored to specific design requirements, including full-scan, boundary scan, and memory test strategies.
Design and implement robust DFT infrastructure, including scan chains, compression logic, MBIST, BIST, JTAG, and other test mechanisms.
Generate high-quality ATPG test vectors for logic and memory, and analyze DFT coverage to ensure thorough fault detection and diagnostic capability.
Perform MBIST verification including simulation of memory test algorithms, fault modeling, and debug of failing patterns.
Verify test patterns using gate-level simulations to identify and address functional or timing-related issues.
Collaborate closely with STA, physical design, power, and memory compiler teams to debug and resolve DFT/MBIST-related challenges.
Work in partnership with test engineers to bring up scan and MBIST vectors on silicon, support silicon debug, and ensure successful production testing.

Fortell, San Francisco Bay Area, CA

$160K–$300K

a year

This base pay is near the median for principal hardware and robotics jobs in the Bay Area.

We compare the middle of each posted range. This is base pay as posted. The group does not include this job.

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Develop, architect and implement comprehensive DFT structures tailored to specific design requirements, including full-scan, boundary scan, and memory test strategies.
Design and implement robust DFT infrastructure, including scan chains, compression logic, MBIST, BIST, JTAG, and other test mechanisms.
Generate high-quality ATPG test vectors for logic and memory, and analyze DFT coverage to ensure thorough fault detection and diagnostic capability.
Perform MBIST verification including simulation of memory test algorithms, fault modeling, and debug of failing patterns.
Verify test patterns using gate-level simulations to identify and address functional or timing-related issues.
Collaborate closely with STA, physical design, power, and memory compiler teams to debug and resolve DFT/MBIST-related challenges.
Work in partnership with test engineers to bring up scan and MBIST vectors on silicon, support silicon debug, and ensure successful production testing.