What we need
A Senior DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon.
The ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. The ideal candidate is also knowledgeable about DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes. Should have experience with gate-level simulation and tester pattern formats such as STIL.
Required Skills and Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically
- Strong hands-on experience with UVM-based or similar verification methodologies
- Proficiency in SystemVerilog
- Experience in scripting (preferably Python) and automation
- Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
- Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent)
- Solid understanding of digital design fundamentals
- Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G)
- Strong analytical and problem-solving skills
- Clear written and verbal communication skills for cross-functional collaboration
- High attention to detail and ability to deliver reliable, high-quality verification outcomes
- Ability to work independently and manage tasks to completion