DFT (Design For Test) Engineer

Etched, San Jose

What you will do

Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.
Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle.
Analyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability.
Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features.

Etched, San Jose

Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.
Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle.
Analyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability.
Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features.