DFT Engineer

A self-improving chip design system is only as good as the silicon it produces, and silicon only counts once it has been tested, screened, and shipped. We are hiring a DFT engineer who treats testability as a first-class design discipline: someone who has architected the scan, MBIST, and boundary-scan infrastructure for complex chips at advanced nodes, generated and signed off the patterns that qualified them, and then stood at the tester when first silicon came back. Your expertise will teach our systems how to reason about test coverage, test cost, and yield, and you will use those systems to build real silicon.

You will own DFT end to end at Ricursive: DFT architecture and insertion, MBIST planning, fault-model analysis, and ATPG signoff in pre-silicon, then hands-on CP, FT, and SLT bring-up with our foundry and OSAT partners in post-silicon. You will work shoulder to shoulder with the RTL, DV, and physical design engineers, flex into RTL and DV work when the program needs it, and bring AI tools into the traditional DFT flow wherever they make the work faster or the silicon better. As part of a small team, you will have the opportunity to define our foundational DFT methodology and infrastructure from the ground up.