Timing & Power Analysis CAD Engineer
Marvell, Bangalore
What you need
- B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related field.
- 6 to 10 years of hands-on experience in CAD flow development or power analysis in the semiconductor industry (level-dependent).
- Proven experience with Synopsys PrimeTime & PrimePower (gate-level and/or RTL-level power analysis).
- Solid understanding of timing concepts
- Understanding of advanced node timing effects and variation formats (LVF, POCV & AOCV etc)
- Experience in correlating timing QoR between P&R and signoff timing engine
- Solid understanding of power analysis concepts: dynamic power, leakage, glitch power, clock gating efficiency (CGE).
- Experience with FSDB/VCD/SAIF activity file generation and annotation flows.
- Familiarity with UPF/CPF power intent and multi-voltage design methodologies.