AI Accelerator Physical Design Engineer - Full Time

• Own physical implementation of accelerator blocks and top level: synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing
• Develop floorplans for repeated compute tiles, large SRAM arrays, and high-bandwidth data movement, balancing congestion, wire length, and utilization
• Close timing, power, and area (PPA) targets, including optimization of datapath-heavy and high-fanout structures
• Manage power delivery and density: power grid design, IR-drop and electromigration analysis, and thermal-aware implementation
• Implement low-power techniques such as clock gating, power gating, multi-Vt, and multi-voltage domains
• Run static timing analysis, signal-integrity, and physical verification (DRC/LVS) signoff across corners and modes
• Partition and implement hierarchical designs, including budgeting and integration of replicated blocks
• Work with architecture, RTL, DFT, and verification teams to co-optimize design for physical implementability
• Develop and maintain automation for flows, regressions, and QoR tracking
• Support silicon bring-up and correlate post-silicon results with pre-silicon predictions

Read the job posting on the Rosaic Labs site

Source: the Rosaic Labs Lever job board. We last checked this job 7 h ago. We first saw it 4 days ago. A job on a job board does not always mean that the team interviews people now. We found this job board in a public list. We did not yet compare it with the careers page of the company.