Design Verification Engineer
Upscale, US - Santa Clara, CA
What you will do
- Design, develop, and maintain robust verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.
- Develop comprehensive verification plans and create test cases to ensure complete functional coverage.
- Verify RTL designs at both block and chip levels using directed testing, constrained-random verification, assertion-based verification (ABV), formal verification techniques, and functional coverage methodologies.
- Perform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations to validate design quality and completeness.