R&D Engineer Physical Design

We are seeking an experienced ASIC Implementation Engineer to drive physical design execution on next-generation, high-complexity system-on-chip (SoC) architectures across advanced FinFET process nodes (e.g., 5nm, 3nm, 2nm).

In this role, you will lead critical implementation disciplines—from floorplanning through to clocking, power integrity, and final tapeout. You will work closely with architecture, RTL, CAD, and package engineering teams, as well as external foundry partners and customers worldwide, to ensure first-pass silicon success under demanding performance, power, and area (PPA) constraints.