R&D Engineer Physical Design

We are looking for an experienced STA & Timing Closure Engineer to lead static timing analysis and signoff execution for high-complexity, multi-GHz System-on-Chip (SoC) architectures on advanced FinFET and GAA nodes (5nm, 3nm, 2nm). In this role, you will take end-to-end ownership of full-chip and block-level timing closure across complex multi-voltage, multi-frequency domains, ensuring first-pass silicon success while maximizing Performance, Power, and Area (PPA) metrics. Key Responsibilities

• Multi-Mode Multi-Corner (MMMC) STA: