IC Design Verification Engineer

You verify the blocks and subsystems of a first-of-its-kind chiplet — building UVM testbenches, writing tests, and driving coverage to closure. Guided by the verification plan and methodology, you take assigned blocks from testbench bring-up through coverage signoff, and help debug across simulation and emulation. It’s a hands-on role with room to grow your scope as the team and the chip mature.

• Build and extend UVM testbenches (agents, sequences, scoreboards) for assigned blocks and subsystems.
• Write directed and constrained-random tests; develop functional coverage and drive it to closure.