Senior Verification Engineer - HSIO Cluster and SOC

You will develop verification components and API's for cluster and system level test benches. These will verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC.

During the course of a project, you will drive the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using SV, C/C++ methodology
• Define test plans, tests and verification infrastructure for clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
• Implement functional coverage and own SOC level verification closure
• Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust

• BTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have over 5 years of experience in verification closure of complex units, sub-systems, or SOC level verification.
• Proven experience in High Speed IO verification (UFS/PCIE/XUSB), knowledge of 10G/1G Ethernet MAC and Switch
• Experience in the latest verification methodologies like SV and UVM
• Good debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug
• Good interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization

Ways to stand out from the crowd

• Exposure on using AI (like Claude or Cursor) extensively for code development would be a big plus
• A mentality towards constant improvement and looking to build a multiplier effect through your work and automation
• Exposure to Formal verification would be excellent

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