Sr/Staff Engineer, Design Verification,System IP

Who You Are

• You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM.
• You enjoy debugging complex design and verification issues and working closely with cross-functional teams.
• You’re comfortable building verification environments from scratch and driving coverage closure.
• You have familiarity with standard bus protocols and modern verification tools.

What We Need

• Experience owning block or subsystem-level verification from test planning to sign-off.
• Strong understanding of constrained-random verification, coverage analysis, and regression debugging.
• Familiarity with protocols such as AXI, ACE, CHI, or PCIe.
• Scripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements.

• Verification of advanced CPU and memory-management related IPs used in AI/ML systems.
• Building scalable UVM environments and improving verification methodologies.
• Collaborating across architecture, RTL, and validation teams throughout the development cycle.
• Using Automation and AI-assisted tools to improve productivity and debug efficiency

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S.

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.