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Principal Verification Engineer

Astera Labs, San Jose, California +1

Astera Labs has this job in 1 other place

San Jose, California, United States

Posted pay

$185K–$230K

a year

Location: San Jose, California +1
Work type: Not given
Level: Principal
Experience: 8+ years
Skills in the job text: SystemVerilog
Posted: 15 days ago
Last check: 27 min ago
Job type: Software engineering, Inference & ML systems

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Astera Labs

About Astera Labs: funding, hiring and pay

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The role

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

What you will do

Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
Work with RTL designers to troubleshoot and resolve design issues.
Drive verification strategy and methodology for SoCs in server and networking applications.

What you need

Bachelor’s degree in Electrical Engineering (Master’s preferred).
8+ years of experience in SoC verification, particularly for server and networking applications.
Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
Proficiency with industry-standard simulators, version control, and regression systems.
Strong debugging and coverage analysis skills.
Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
Familiarity with verification of switching architectures, including packet processing and forwarding engines.
Excellent communication skills and ability to work independently with minimal supervision.

Nice to have

Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
Knowledge of Ethernet/PCIe switching and central buffer architectures.
Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Astera Labs

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Read the job posting on the Astera Labs site

Source: the Astera Labs Greenhouse job board. We last checked this job 27 min ago. We first saw it 5 days ago. A job on a job board does not always mean that the team interviews people now. We found this job board in a public list. We did not yet compare it with the careers page of the company.

Astera Labs

Open tech jobs: 106
With posted pay: 58%
Median posted base: $185K–$240K

About Astera Labs: funding, hiring and pay

Compared with similar jobs

This base pay is below the median for principal software engineering jobs in the Bay Area.

Median: $280K a year
Other jobs in the group: 223

We compare the middle of each posted range. This is base pay as posted. The group does not include this job.