Teach Lead Physical Design Engineer
Astera Labs, Singapore, Singapore +1
The role
We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes
What you will do
- Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes.
- Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
- Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
- Work on key physical design areas including:
- EM/IR analysis and power grid optimization
- Congestion analysis and mitigation