Design Engineering Intern (CCE2)

Join the CCE2 Design Engineering team and gain hands-on experience developing digital logic for advanced connectivity ASICs. You’ll work at the intersection of architecture, RTL, simulation, synthesis, verification, physical design, DFT, and firmware to help turn product requirements into robust, implementable hardware.

This internship is designed for someone who enjoys understanding how a system should work, expressing that behavior in RTL, and debugging the difference between intended and observed results. You’ll work with experienced design engineers on a meaningful project involving a block, subsystem, interface, datapath, control path, or reusable design infrastructure.

• Learn the product architecture, microarchitecture, design methodology, development environment, tools, and project workflow needed to contribute effectively.
• Read architecture, interface, microarchitecture, and product-requirement documentation and translate requirements into clear design behavior.
• Design, implement, modify, and document synthesizable RTL in Verilog or SystemVerilog under engineering guidance.
• Contribute to datapaths, control logic, state machines, register interfaces, configuration and status logic, error handling, arbitration, buffering, or other digital design functions.
• Work with interface and connectivity logic for technologies such as PCIe, CXL, UALink, Ethernet, SERDES, or related high-speed systems as appropriate for the project.
• Develop or update design specifications, block diagrams, interface definitions, register descriptions, timing assumptions, and design documentation.
• Run simulations and use waveforms, logs, assertions, and regression results to debug RTL behavior and verify design changes.
• Support lint, CDC/RDC, synthesis, formal, low-power, or related design-quality checks and investigate issues with guidance from experienced engineers.
• Collaborate with Design Verification to make interfaces and behavior testable, review coverage or failures, and resolve issues found during verification.
• Work with physical design, DFT, emulation, firmware, validation, and architecture teams to understand constraints, handoffs, and implementation impact.
• Contribute to scripts, configuration, test collateral, reports, code reviews, issue tracking, and design-flow improvements.
• Deliver assigned design work in a reproducible, reviewable, and well-documented state and present your project, results, and key learnings at the end of the internship.

• Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.
• Foundational understanding of digital logic, RTL, computer architecture, finite-state machines, computer arithmetic, or hardware interfaces.
• Experience with Verilog, SystemVerilog, VHDL, C/C++, Python, or another language used in digital design and automation.
• Curiosity about how complex silicon designs work and a methodical approach to translating requirements into testable, maintainable logic.
• Comfort learning in Linux and working with command-line tools, source control, technical specifications, logs, waveforms, and development scripts.
• Ability to ask focused questions, communicate assumptions and blockers, accept design feedback, and follow through on commitments.
• Ownership, learning agility, persistence, and a collaborative mindset in a fast-moving silicon-development environment.

• RTL design, simulation, assertions, lint, CDC/RDC, synthesis, formal analysis, or design-for-test concepts.
• SystemVerilog interfaces, parameterized modules, FIFOs, arbiters, pipelines, state machines, register maps, or bus protocols.
• PCIe, CXL, UALink, Ethernet, SERDES, retimers, switches, memory systems, SoC design, or other high-speed connectivity technologies.
• EDA tools such as VCS, Verdi, DVE, Design Compiler, Fusion Compiler, or comparable tools.
• Python, Tcl, Bash, or other scripting for automation, report parsing, regression support, or data analysis.
• Emulation, FPGA prototyping, gate-level simulation, timing constraints, power-aware design, or hardware bring-up.
• Git, Bitbucket, Jira, Confluence, Slurm, or similar collaborative engineering workflows.

Internship experience and compensation

This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.

Astera Labs · San Jose, CA · Internship · On-site

Astera Labs builds connectivity solutions that help power modern AI infrastructure. Compute Connectivity Engineering 2 (CCE2) develops complex silicon and connectivity products for high-performance systems, including technologies such as PCIe, CXL, and UALink.