Experience - 6–12 years
Job Summary
We are looking for a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams.
The candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to establish efficient and reusable methodologies.
Required Technical Skills
- Strong experience in verification methodology, CAD, and automation.
- Strong programming/scripting skills in Python, Tcl, Perl, Shell, and preferably C/C++.
- Strong understanding of SystemVerilog/UVM.
- Experience with simulation tools such as VCS, Xcelium, Questa, or equivalent.
- Experience building and maintaining regression infrastructure.
- Strong knowledge of coverage collection and analysis.
- Understanding of verification flows including:
- Simulation
- UVM
- Lint
- CDC/RDC
- Formal
- Code/functional coverage
- Regression
- Debug
- Strong Linux/Unix environment experience.
- Excellent automation and problem-solving skills.
Education
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, Computer Engineering, VLSI, or a related discipline.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.