Manager/Director of Hardware Engineering

• Team Leadership: Directly manage, mentor, and grow a team of 8-12 RTL and DV engineers.
• Execution & Delivery: Drive the development of high-speed interconnect IP from microarchitecture specifications to RTL implementation and tape-out.
• Verification Excellence: Oversee the development of robust, coverage-driven verification test plans, UVM/OVM environments, and emulation platforms.
• Cross-Functional Collaboration: Work closely with architecture, physical design, and system teams to balance power, performance, area (PPA), and timing requirements.
• Process Optimization: Define and establish engineering metrics, standard methodologies, and agile project management tools to meet strict tape-out milestones.

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8+ years of industry experience in ASIC/IP development, with at least 2-3 years in a technical leadership or management role.
• Technical Domain: Strong background in high-speed protocols (e.g., PCIe, UCIe, CXL, Ethernet, or advanced SerDes).
• Design Skills: Proficiency in SystemVerilog, Verilog, and industry-standard EDA simulation/synthesis flows.
• Verification Skills: Deep understanding of modern verification methodologies (UVM/OVM), constrained random testing, formal verification, and coverage analysis.
• Startup Mindset: Highly adaptable, proactive problem-solver with a proven track record of delivering results in a dynamic, fast-moving environment.

• Salary commensurate with experience
• Performance incentives
• Comprehensive medical, dental, and vision benefits
• 401(k) retirement plan
• Equity

Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.