RTL Engineer
DensityAI, Mountain View, CA +1
The role
Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.
What you will do
- Own RTL design of digital blocks/subsystems for our accelerator — microarchitecture definition, SystemVerilog implementation, and integration
- Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
- Drive microarchitecture trade-offs — pipelining, datapath vs. control, clock/power gating — for high-performance, low-power design
- Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
- Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff