Design Verification Engineer - Interface IP
Etched, San Jose
Etched has this job in 1 other place
What you will do
- End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
- Understand vendor IP configurations and handle handshake with internal IP team
- Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
- Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.