Physical Design Engineer - Full Chip Implementation

Etched, San Jose

What you will do

Own full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.
Own timing constraints and hierarchical timing budgeting between top level and blocks.
Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.

Etched, San Jose

Own full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.
Own timing constraints and hierarchical timing budgeting between top level and blocks.
Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.