Cryo-CMOS Application Engineering Lead

IonQ, Oxford, England, United Kingdom +1

The role

We are looking for a Cryo-CMOS Application Engineering Lead to join our Cryo-CMOS IC team at IonQ Oxford. You will own the path from chip description to proven silicon for the analogue and mixed-signal ASICs in our trapped-ion quantum processors, turning each chip’s specification and design description into a silicon validation plan that our silicon evaluation engineers run their measurements against.

This is a hands-on leadership role. You will lead the silicon evaluation engineers and work at the bench alongside them, help establish our evaluation laboratory, coordinate with equipment suppliers and provide the evidence needed for confident silicon acceptance decisions. The work covers room temperature and cryogenic temperatures, on packaged parts, chip-on-board assemblies and bare die on a cryogenic probe station.

All jobs

Cryo-CMOS Application Engineering Lead

IonQ, Oxford, England, United Kingdom +1

The role

What you will do

Responsibilities

You will be the link between chip design, the laboratory and the teams who integrate our chips into the quantum processor, working closely with analogue and digital design, verification, modelling, firmware and systems engineers. You will set the standard for how we plan, measure and report, and build a capability that improves across successive ASIC generations.

Key responsibilities include

●Convert chip descriptions (specifications, architecture and design documents, register maps) into silicon validation plans with measurable tests, conditions, limits and acceptance criteria; maintain traceability from requirements to tests, results and unresolved risks. ●Lead the silicon evaluation engineers who run the plan: set priorities, assign and review work, coach and develop the team, and stay hands-on at the bench. ●Help establish and run the evaluation laboratory: define room-temperature and cryogenic measurement capability, specify equipment, and set calibration, safety and operating practice. ●Coordinate with equipment suppliers and internal procurement, from specification and evaluation through delivery, installation, acceptance and support. ●Lead first-silicon bring-up and characterisation of sample-and-hold and switch arrays, DACs, ADCs, references, amplifiers, regulators, clocking and device-level test structures, including bare-die probing and the cold signal chain; establish calibration, measurement uncertainty and repeatability before interpreting margins. ●Direct the development of validation boards, fixtures and reusable Python automation, with version-controlled tests, configuration records and reproducible data analysis. ●Drive failures to root cause, separating silicon defects from board, firmware and test artefacts; correlate measurements with simulations and device models, and feed findings and testability requirements back to design before the next tape-out. ●Own validation readiness reviews and the silicon acceptance report; present coverage, margins, defects and recommendations to the Cryo-CMOS IC Lead and programme stakeholders. ●Plan equipment, resource and schedule needs; coordinate validation with external design partners, the foundry and other IonQ sites under one controlled plan and a shared, traceable dataset.

Cryo-CMOS Application Engineering Lead

The role

Cryo-CMOS Application Engineering Lead

The role

What you will do

Responsibilities

Key responsibilities include

What you need

You'd be a great fit with

Pay and benefits

About IonQ

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