Senior ASIC Physical Design Engineer, Netlisting

NVIDIA, US, CA, Santa Clara +1

What you will do

You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.

NVIDIA, US, CA, Santa Clara +1

$136K–$265K

a year

This base pay is near the median for senior hardware and robotics jobs in the Bay Area.

We compare the middle of each posted range. This is base pay as posted. The group does not include this job.

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You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.