- Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
- Proficiency in Timing and Static Timing Analysis (STA).
- Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management.
- Expertise with industry standard EDA and timing convergence tools.
Ways to stand out from the crowd
- Proven experience in timing convergence for ASICs, CPUs, GPUs or Network processors.
- Knowledge of deep sub-micron process nodes.
- Proficiency in AI/LLM and programming languages.
- Experience in physical design and optimization e.g., synthesis, floorplanning, placement, CTS, routing, power, etc. is a plus.
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.