ASIC Design Verification Engineer - Specs
Snap, Eindhoven - Netherlands
What you will do
- Own verification of complex IP blocks and subsystems from specification through sign-off.
- Build and maintain UVM/SystemVerilog verification environments.
- Develop constrained-random tests, coverage plans, assertions, and verification strategies.
- Drive functional and code coverage to closure.
- Partner closely with design, architecture, firmware, and other engineering teams to refine requirements and debug issues.
- Improve verification methodologies, tools, automation, and workflows across the team.
- Explore practical ways to use AI-assisted tools to improve verification productivity and effectiveness.