Senior Principal Engineer - Design Verification

We are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive-scale networking SoCs. This is a high-impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross-functional alignment from architecture to post-silicon, and pioneering next-generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.