Senior RTL Design Engineer

We are looking for a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC: the compute fabric's on-chip interconnect and memory interfaces, low-power and always-on logic, and standard peripheral IP (RISC-V, NVM, I2S, I2C). As a hands-on individual contributor, you will take blocks from microarchitecture spec through clean, synthesis-ready RTL, working closely with architects, the design lead, DV, physical design, and firmware to tape out an industry-leading ultra-low-power SoC.