Substrate IC Package Layout Design Engineer
Etched, San Jose
What you will do
- IC Substrate Layout Design
- Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
- Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.
- Ensure robust power delivery designs capable of supporting >700W custom silicon solutions.
- High-Speed Signal Routing & Integrity
- Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.
- Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.
- Advanced Packaging & CoWoS Integration
- Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.
- Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.
