Silicon Packaging Design Engineer

• Design and develop microelectronic package substrates from architecture definition through final tapeout.
• Create and optimize physical package layouts, including high-density routing solutions that meet electrical, mechanical, thermal, and manufacturability requirements.
• Perform substrate feasibility, fit, and routing studies to evaluate design tradeoffs involving performance, complexity, cost, and schedule.
• Define, implement, and maintain substrate design rules while conducting design reviews with internal and external stakeholders.
• Analyze and resolve design rule check (DRC) violations and other layout-related issues to ensure design quality and robustness.
• Collaborate with silicon, package, board, signal integrity, power integrity, and manufacturing teams to optimize pinouts and system-level connectivity.
• Drive continuous improvements in package design methodologies, automation, and best practices.
• Generate and maintain design documentation, technical reports, and engineering deliverables within product lifecycle management systems.
• Support package bring-up, qualification, and debug activities as needed.

Qualifications

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• US Citizenship required.
• Ability to obtain US Government TS/SCI Security Clearance.
• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related engineering discipline and 6+ months of experience.
• Experience or academic exposure with microelectronic package or PCB physical layout design and manufacturing process.
• Experience with with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
• Experience with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion.

• Post Graduate degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related engineering discipline.
• Active US Government TS/SCI Security Clearance.
• Experience with semiconductor package substrate design, package I/O planning, and high-density routing technologies.
• Knowledge of advanced packaging technologies such as flip-chip, 2.5D, 3D packaging, chiplets, embedded bridge, or high-bandwidth interconnect solutions.
• Familiarity with package electrical analysis and simulation tools including HyperLynx, PowerDC, Ansys HFSS, and Ansys Q3D.
• Experience using package automation and productivity tools such as Package Layout Automation (PLA) and FIELD.
• Programming or scripting experience using Python, VB, C/C++, or similar languages to drive design automation and workflow improvements.
• Proven ability to troubleshoot complex design challenges and develop innovative engineering solutions in a fast-paced environment.

Why Intel

At Intel, you'll work alongside world-class engineers developing technologies that power everything from artificial intelligence and cloud computing to next-generation client and edge platforms. You'll have the opportunity to solve complex technical challenges, influence leading-edge products, and accelerate your career while helping shape the future of semiconductor innovation

Job Type

Experienced Hire

Shift

Position of Trust N/A

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $91,150.00-172,860.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

• ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.