IC/RTL Design Engineer
Lumilens, San Jose
What you will do
- Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
- Design and implement front-end RTL blocks in SystemVerilog — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
- Integrate IP and support parameterization for configurability.
- Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.
- Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.
- Power- and timing-aware design — managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.