Senior STA Engineer

Astera Labs, Ahmedabad, Gujarat, India +1

What you will do

Own STA and timing signoff activities from synthesis through physical design and tape-out.
Perform MCMM/MMMC timing analysis across all functional and test modes.
Analyze and debug setup, hold, recovery, removal, min/max, and clock-related violations.
Develop, review, and validate SDC constraints, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.
Perform detailed clock tree and clock timing analysis, including skew, latency, uncertainty, jitter, and clock reconvergence.
Drive timing closure in collaboration with RTL, synthesis, physical design, and ECO teams.
Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions.